Why pre-screen MEMS engineers before the technical panel
In this field the design is the easy part. Process tolerances, residual stress, stiction and packaging all move a device away from what the simulation predicted, and yield is where the money is decided. Engineers worth hiring have been through a process development cycle and know what limited their yield. A short screen asks that question, which separates fabrication experience from modelling.
What actually matters when screening Microelectromechanical Systems Engineer candidates
- 01
Technical depth
Probe depth in MEMS device physics: squeeze-film damping, pull-in voltage, residual stress control, DRIE aspect ratios, SOI versus bulk process choices, and COMSOL or ANSYS modal simulation.
- 02
Work that shipped
Ask which MEMS devices reached tape-out or volume: accelerometers, gyros, micromirrors, pMUTs. Check their role in PDK development, wafer-level bonding, and yield ramp figures.
- 03
Diagnosis under uncertainty
Test failure analysis instinct: stiction, particle contamination, drift over temperature, package-induced stress. Look for use of DOE, SEM cross-sections, laser Doppler vibrometry, and burn-in data.
- 04
Working across the org
Assess handoffs to ASIC designers, process integration engineers, and foundry partners; look for ownership of PCM specs, PDK release notes, and reliability qualification with test teams.
Pre-screening questions to ask Microelectromechanical Systems Engineer candidates
12 questions grouped by what they test. Ask the same set in every screen and score answers on a consistent scale, or send them as an async video screen and compare answers side by side.
Devices they shipped
3 questions01Have you contributed to the design or manufacture of devices in this field?
Listen forDevices that reached manufacture with volumes described, and their own contribution stated clearly.
Designs that stopped at simulation, or contribution described at team level with no personal scope.
02Do you have experience designing sensors and actuators at this scale?
Listen forTransduction principle chosen for the application, with sensitivity and noise floor reasoned through.
Devices described by structure alone, or performance figures quoted from a reference design.
03Do you have experience with packaging and integration for these products?
Listen forPackage stress and its effect on device performance understood, with hermeticity considered where needed.
Packaging treated as a downstream problem, or package-induced drift never encountered.
Fabrication reality
3 questions04Can you describe your experience with design software for these devices?
Listen forLayouts drawn against a specific process design rule set rather than in the abstract.
Design work with no process constraints applied, or layouts never taken to a mask set.
05Have you worked with simulation software for design in this field?
Listen forSimulation results correlated against measured devices, with the divergence understood and explained.
Simulation accepted without measurement, or model assumptions never validated against silicon.
06Can you explain your experience with the materials used in these devices?
Listen forMaterial properties at these scales understood, including residual stress and thin film behaviour.
Bulk material properties assumed at microscale, or residual stress not considered in design.
Packaging and reliability
3 questions07What is your experience with fabrication technologies and processes?
Listen forProcess steps understood in detail, with the tolerance of each and its effect on the device known.
Processes named without understanding their variation, or fabrication treated as a service.
08What is your experience with microfabrication in creating these devices?
Listen forHands-on process work including etch and release steps, with the practical failure modes described.
No time spent in a fabrication facility, or release and stiction problems never encountered.
09What is your understanding of cleanroom protocols and procedures?
Listen forContamination control treated as fundamental, with particle sources and gowning discipline understood.
Cleanroom practice described as gowning up, or contamination not linked to yield loss.
Characterised properly
3 questions10Do you have experience with reliability and failure modes in these devices?
Listen forSpecific failure mechanisms encountered, with qualification testing performed against real use conditions.
Reliability assumed from design margin, or no device they have taken through qualification.
11Do you have knowledge of testing and characterising these devices?
Listen forWafer-level and packaged testing understood, with measurement uncertainty accounted for at these scales.
Characterisation delegated entirely, or measurement uncertainty not considered in the results.
12Do you have knowledge of quality standards and regulation in this manufacturing?
Listen forStandards relevant to the end market understood, with traceability and process control maintained.
Standards treated as paperwork, or requirements for the end application not known.
How to score responses
Score every candidate on the same four criteria immediately after the screen. At this stage you are shortlisting for panel interviews, not making the final call.
Technical depth
35%5Explains device behaviour from first principles, links simulated resonance and damping to measured Q, names specific mask and etch constraints.
Work that shipped
30%5Names shipped parts, their foundry or fab, wafer counts, yield improvement from split-lot experiments, and their own contribution to each step.
Diagnosis under uncertainty
20%5Walks through a real yield or drift excursion, isolates root cause with cross-section or vibrometry evidence, states what the fix changed.
Working across the org
15%5Describes concrete negotiations with fab and ASIC counterparts, documents interface specs, keeps schedules aligned across long fab cycle times.
The design is the easy part; process tolerance and packaging decide the yield. A one-way video screen asks what limited theirs.
Try it on HirevireScreening FAQ
Process basics
How long should a pre-screening round for this role take?
Fifteen minutes across eight to ten questions, answered async. Enough to establish devices that reached manufacture, test their fabrication knowledge, and check reliability and test practice.
How much should simulation experience count?
Less than fabrication experience. Simulation tools are learnable; knowing which process variations will move your device out of specification takes years in a working fabrication facility.
Evaluating answers
What is the strongest signal when screening this role?
Knowing what limited their yield. Engineers who have taken a device through manufacture answer immediately with a process step. Anyone who has only designed will describe the design instead.
How do I judge their reliability thinking?
Ask about failure modes they have seen. Real answers cover stiction, fatigue, particle contamination or package stress. Anyone with no failure story has not run a device through qualification.
Go deeper on this role
Sanat has been hiring since 2012 and watching the recruitment industry change up close ever since, and turned that screening process into Hirevire's video screening platform. LinkedIn
