Why pre-screen semiconductor process engineers before the on-site fab loop
Pre-screening semiconductor process engineers protects the most expensive interview loop you run. Applicants arrive from university cleanrooms, national labs, equipment suppliers and high-volume fabs, and a resume reads the same for all four: it lists etch, PVD, CMP and DOE without saying who owned the recipe, at what wafer volume, or whether anything shipped. A ten minute screen surfaces the tool platforms they actually ran, the yield numbers they can defend, and whether they can explain the physics behind a recipe knob without notes.
What actually matters when screening Semiconductor Process Engineer candidates
- 01
Technical depth
Probe command of the specific process modules they claim: lithography, etch, deposition, implant, CMP, and the physics driving each.
- 02
Work that shipped
Look for processes that ran in a real fab at volume, with yield and cycle-time numbers attached.
- 03
Diagnosis under uncertainty
Test how they chase a yield excursion to root cause when the signal is noisy and the fab is still running.
- 04
Working across the org
Check how they work with equipment vendors, integration, and manufacturing when a process change affects everyone downstream.
Pre-screening questions to ask Semiconductor Process Engineer candidates
12 questions grouped by what they test. Ask the same set in every screen and score answers on a consistent scale, or send them as an async video screen and compare answers side by side.
Process module depth
4 questions01Which process modules have you personally owned: deposition, etch, photolithography or CMP? Tell me about the tool platform and the recipes you were responsible for.
Listen forNamed platforms and specific knobs, for example chamber pressure and bias power on an etcher or slurry and downforce on a polisher, with wafer size and volume.
They list every module equally and cannot say which recipes they owned or which tools they qualified.
02Do you have hands-on process development experience in lithography or etch, and what did you take from first pass to a released recipe?
Listen forA concrete development path: split matrix, process window definition, tool qualification, spec limits set, then release into production with SPC charts attached.
Development experience stops at lab coupons or single wafers with no path to a released, monitored production recipe.
03In about 60 seconds, explain how a semiconductor device works and how your process module affects its electrical behaviour.
Listen forClear link from process to device: gate dielectric thickness or implant dose to threshold voltage, contact profile to resistance, explained without jargon padding.
They recite textbook definitions with no connection between a process parameter and a measurable device or electrical result.
04Which semiconductor materials have you worked with most closely, and what made them difficult to process?
Listen forMaterial-specific problems: high-k and metal gate integration, copper barrier and seed coverage, SiC or GaN handling, low-k damage during etch or clean.
Generic answers about silicon wafers with no material-driven process constraint or failure mode described.
Yield data and methods
4 questions05What has your exposure to yield enhancement looked like? Walk me through one yield number you moved and by how much.
Listen forA named loss mechanism, the inline or e-test signal used, the change made, and yield points or defect density improvement with the timeframe.
Yield work described only as team meetings and dashboards, with no improvement they can quantify or claim.
06How have you used statistical process control on a production process? Which charts and limits did you set and act on?
Listen forWorking use of X-bar and R or individuals charts, Cpk targets, out-of-control action plans, and a real decision to hold or disposition lots.
They know SPC as a definition only and cannot describe a limit they set or an alarm they responded to.
07How familiar are you with design of experiments in semiconductor processing? Describe a DOE you designed and what it told you.
Listen forFactors, levels, response variables and confounding handled deliberately, with software named (JMP, Minitab) and a decision that came out of the analysis.
They change one variable at a time, or describe a DOE run for them by someone else with no interpretation of results.
08Which failure analysis tools have you used on semiconductor devices, and what did they let you conclude?
Listen forHands-on requests or interpretation of SEM, TEM cross-sections, FIB, EDX, defect inspection or e-test data tied to a specific root cause conclusion.
They name analysis techniques but cannot describe a single image or spectrum that changed their diagnosis.
Diagnosis and collaboration
2 questions09Describe a time you solved a complex problem in semiconductor processing when the signal was noisy and the fab was still running.
Listen forStructured commonality analysis across tools, chambers and lots, hypotheses ruled out with data, containment while production continued, then verified root cause.
They jump to a fix with no data trail, or blame the tool vendor without ruling out process and integration causes.
10What innovation or efficiency have you introduced in a past semiconductor role, and how did it hold up in production?
Listen forA change that survived handoff: cycle time cut per layer, chamber clean frequency reduced, rework eliminated, with buy-in from integration, equipment and manufacturing named.
Ideas that never left a slide deck, or improvements with no downstream owner and no sustained measurement.
Cleanroom and logistics
2 questions11Talk me through your experience working in cleanroom environments and how much of your week was spent gowned on the floor.
Listen forRealistic hours in a Class 1 to Class 100 fab, gowning discipline, tool time alongside technicians, and comfort with shift or on-call escalation.
Little or no time gowned, or reluctance to spend regular hours on the fab floor with tools and technicians.
12What do you do to keep your work environment safe when handling process chemicals and gases?
Listen forNamed hazards and controls: hydrofluoric acid handling, silane or chlorine gas lines, lockout tagout, PPE, and how they respond to an alarm.
Vague commitment to safety culture with no specific chemical, gas hazard, or procedure they have actually followed.
How to score responses
Score every candidate on the same four criteria immediately after the screen. At this stage you are shortlisting for panel interviews, not making the final call.
Technical depth
35%5Explains the process physics and the tolerances they designed against, and defends decisions under follow-up.
Work that shipped
30%5Names processes that reached production, with measured yield, cycle time, or cost improvement they owned.
Diagnosis under uncertainty
20%5Isolates variables systematically on a real excursion, and can say what they ruled out and why.
Working across the org
15%5Negotiates process changes across integration and vendors, and documents them so others can act.
Async video lets you hear whether a candidate can explain etch selectivity or a litho process window out loud, unscripted, the way they would in a yield meeting. Screen recordings also let them walk you through a wafer map or Pareto chart.
Try it on HirevireScreening FAQ
Process basics
How long should a pre-screening interview for a process engineer be?
Keep it to ten or twelve minutes of recorded answers, roughly eight to twelve questions with two or three asked as audio. That is enough to hear module depth and one excursion story end to end. Save wafer map reviews, integration scenarios and cleanroom site visits for the on-site loop with your module owners.
What should you ask if the candidate comes from a university cleanroom rather than a production fab?
Ask what wafer size and volume they ran, how many lots per week, and whether any recipe went to a customer or a production line. Research cleanroom work builds real hands-on tool skill on litho, etch and deposition, but it rarely teaches SPC discipline, lot dispositioning, or working inside a running fab's change control.
Evaluating answers
How do you tell real process depth from buzzword answers?
Strong answers name the tool platform, the knobs and the physics together: chamber pressure and bias power for an etch profile, dose and focus for a litho window, downforce and slurry chemistry for CMP. Weak answers stay at the module label, repeat job description phrasing, and cannot say which parameter they moved or why it worked.
What does a good yield excursion answer sound like?
It follows a trail: inline signal or SPC alarm, wafer map and commonality analysis across tools and chambers, hypotheses ruled out with defect inspection or cross-section imaging, then the fix and the yield recovered. Watch for candidates who jump straight to the answer, skip the data, or credit a team without describing their own step.
Go deeper on this role
Sanat has been hiring since 2012 and watching the recruitment industry change up close ever since, and turned that screening process into Hirevire's video screening platform. LinkedIn
